AMD/Xilinx Artix7 XC7A35T/XC7A100T/XC7A200T davinci pro

The baseboard resources of the ALIENTEK DaVinci Pro development board are as follows:

- 1 core board interface, compatible with ALIENTEK A7-35T / A7-100T / A7-200T core boards
- EEPROM chip: AT24C64, capacity: 64Kbit (8K bytes)
- 1 RS485 interface
- 1 CAN interface
- 1 PCIe 2.0 x2 interface
- 2 fiber optic interfaces
- 1 power indicator (blue)
- 4 status indicators (LED0~LED3: red)
- 1 ATK module interface, compatible with ALIENTEK Bluetooth/GPS/MPU6050/RGB LED modules
- 1 standard RGB888 TFT-LCD interface
- 1 OLED/Camera module interface
- 1 USB to UART interface
- 1 USB 2.0 Slave interface
- 1 active buzzer
- 1 XADC interface
- 2 HDMI interfaces: 1 input (using ADV7611 decoder chip solution), 1 output
- 1 TF card interface
- 2 Gigabit Ethernet interfaces
- 1 JTAG debug/download port (10-pin)
- 1 set of 5V power expansion terminals, capable of supplying or receiving power
- 1 set of 3.3V power expansion terminals, capable of supplying or receiving power
- 1 DC power input interface (input voltage range: DC 6V~16V)
- 1 RTC backup battery holder with battery
- 1 RTC real-time clock, using PCF8563 chip
- 1 reset button, usable as a reset signal for FPGA program execution
- 4 function buttons
- 1 capacitive touch button
- 1 power switch controlling the entire board's power
- Two 20x2 expansion headers, providing 72 extended IO pins in total (J4 header is only available with A7-100T core board), each including 3.3V and 5V power interfaces

The A7-35T, A7-100T, and A7-200T core boards share identical peripheral configurations, with the only difference being the main FPGA chip. The detailed resources of these core boards are as follows:

- FPGA Main Controller**: Utilizes Xilinx's Artix-7 series chips:
A7-35T Core Board**: FPGA model XC7A35TFGG484-2I, featuring 33K logic cells (LC) and 1.8 Mbit of BRAM memory.
A7-100T Core Board**: FPGA model XC7A100TFGG484-2I, featuring 101K logic cells (LC) and 4.8 Mbit of BRAM memory.
A7-200T Core Board**: FPGA model XC7A200TFBG484-2I, featuring 215K logic cells (LC) and 13.1 Mbit of BRAM memory.

- 2 x DDR3 SDRAM chips (model: NT5CC128M16IP-DI), each with 2 Gbit capacity, totaling 4 Gbit (512 MB)
- 1 x QSPI FLASH (model: N25Q128), capacity: 128 Mbit (16 MB)
- 1 user LED
- 1 crystal oscillator: 50 MHz, providing the clock for the FPGA
- 1 power indicator
- 1 configuration done indicator (DONE LED)
- 1 Gigabit Ethernet PHY chip: YT8511
- 1 reset button